1. Field of the Invention
The invention relates generally to an interactive terminal computer system having a system bus for communicating between elements of the computer system, and more particularly to an apparatus for permitting the maximum number of substantially concurrent bus cycles without interference with each other.
2. Description of the Prior Art
Most computer systems include one or more terminal systems as an element of the computer system with each terminal system having a number of subsystems each coupled to a central processor unit (CPU) which includes a microprocessor, and to other peripheral devices such as random access memory (RAM), read only memory (ROM), device controllers, etc. Each terminal system with its subsystems may at various times be required to perform various operations such as screen refresh of the cathode ray tube (CRT) of the terminal system, access main memory directly, or perform chip refresh for main memory. To perform these operations communication must be established over the system bus with an element of the computer system. This is generally accomplished by allocating one or more time cycles to the system bus for communicating with one or more elements. Many times requests for access to the system bus came simultaneously and required arbitration to determine which element would receive a cycle on the bus.
One prior art technique for performing this is disclosed in U.S. Pat. No. 4,028,664 by Earnest M. Monahan, et al entitled "Apparatus for Dispatching Data of the Highest Priority Process Having the Highest Priority Channel to a Processor, issued on June 7, 1977 to the same assignee as the instant invention. Another technique for performing this disclosed in U.S. Pat. No. 3,993,981 by Frank V. Cassarino, Jr., et al entitled "Apparatus for Processing Data Transfer Requests in a Data Processing System, issued Nov. 23, 1976, also to the same assignee as the instant invention. However, the prior art devices assign exclusive priority of the bus during a given time cycle. This excludes maximum utilization of the bus during a given time in arbitrating priorities.
What is needed is an improved priority resolver for access to a bus with improved utilization of the bus.
It should be understood that the references cited herein are those of which the applicants are aware and are presented to acquaint the reader with the level of skill in the art and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.